This invention is related generally to integrated circuit (IC) design and fabrication and, more particularly to a CNIOS buffer having a stable output impedance with a controlled current waveform to reduce signal noise, and noise on the IC power and ground nodes.
Each generation of faster chips requires I/O buffer designs which provide better control over supply noise, and faster switching speed of ever-widening data busses. The data transfer rate of digital chips is limited by the achievable clock-to-data propagation delays, which are dominated by output slew rate and noise limitations determined by the output buffer design. Transferring data at gigabits per second rates requires a combination of wide data paths and high frequency signaling. Yet it remains desirable to communicate between digital devices using standard widely-accepted logic levels such as the LVTTL (low voltage transistor transistor logic) I/O interface specification. Chip data output drivers compatible with this standard must be capable of slewing high capacitance loads (many tens of picofarads) through relatively large voltage transitions (&gt;2 volts) at ever increasing speeds. The resulting displacement currents must flow through I/O pin and power/ground pin inductances, causing self-induced voltage spikes which can interfere with device operation.
Contemporary chip packaging technology has not kept pace with the increasing frequency demands, typically interposing several nano-henries of package lead inductance between chips and their board-level power and ground planes. Inductive parasitics introduce noise components, such as "ground bounce", worsen in proportion to the square of switching speed. Since package parasitics have not improved sufficiently to keep up with switching speed requirements, the design of output buffers must be improved to more closely approach the best possible trade-off between switching speed and noise for any given package configuration.
For example, a data bus switching at 100 MHz must slew at a rate of over one volt per nanosecond. Each power and ground pin must typically drive up to eight data pins, each loaded by typically 35 pF of capacitance, through 2 volt excursions within 2 nanoseconds. A linear-ramped (triangular) current/time waveform is the most efficient for transporting maximum charge from a load capacitance in minimal time without exceeding a preset noise voltage limit, since the noise arises from the rate of change of current according to the self-inductance equation v=Ldi/dt. The required voltage slew rate could be obtained by fashioning a triangular current pulse which ramps up linearly from 0 for the entire 2 ns slew time, reaching a peak value determined by: EQU Qcap=N*C*.DELTA.V=.intg.i(t)dt
where N.ident.number of outputs simultaneously driving their capacitive loads C through a common power/ground current path. For a linear current ramp: EQU i(t)=Ipeak*(t-t.sub.0).fwdarw..intg.i(t)dt=Ipeak*.DELTA.t/2.fwdarw.Ipeak =2*N*C*.DELTA.V/.times.t=2*8 drivers*35pF*2v/2ns=0.56 amps
This would result in an induced voltage doublet (noise spike) through typically 3 nanohenries of power/ground self-inductance determined by: EQU Vpeak=Ldi/dt=3nH*0.56A/2ns=.+-.0.84 volts.
In practice, the higher frequency components of the noise doublet will be filtered by the L-R-C network comprising the package power pin inductance, drivers' channel resistance, load capacitances and load pins' inductances, resulting in a damped sinusoidal ringing of the output transition edges. However, the resistances of the switching driver transistors are time-varying. Thus, the peak magnitude and duration of this ringing depends on the details of the output driver transistors' switching transitions between a state which provides a low-channel-impedance current path to the power pin, through a higher-impedance state, to a low-channel-impedance connection to the ground pin. Meanwhile, the load voltage swings (whose rate must be maximized while its overshoots must be limited) affect the time-varying resistive components of the network by changing the operating modes of the nonlinear switching transistors.
The problem is to provide a practical circuit which rapidly charges the load network while controlling and limiting the noise components to prevent system misbehavior. These noise components arise from three main sources, each of which typically places a maximum limit of about 0.4 volts (for LVTTL) on the effective supply noise:
A. multiple switching of inputs at the receiving chip in response to multiple bounces of the output voltage;
B. false-switching of any quiescent (non-switching) outputs which share common power/ground connections with switching outputs; and
C. false-switching of chip inputs or internal logic due to noise coupled to internal power distribution networks through the chip's common substrate and power connections.
Numerous attempts have appeared in the literature to provide circuits which tailor the aforementioned impedance transitions in order to produce faster waveforms. Each has disadvantages however. Some require that the outputs remain non-driven (high-Z) for a period of time prior to going to a valid logic level. However, this sequence of events is intolerable for many digital systems, which strive to minimize the interval during which the outputs are indeterminate. Others reduce the voltage swing to less than the LVTTL requirements. Others draw DC current making them inappropriate for low-standby-power applications. Others require the impractical addition of external components such as resistors or reference voltages. More practical approaches use on-chip resistors to stabilize slew rate, but unfortunately use them in configurations which produce sub-optimal and imprecise shaping of current waveforms, making them incapable of attaining the speed/noise performance levels required by the 100 MHz operation given in the example above.
Another approach has been to subdivide the output buffer into multiple drivers which are activated at successive time intervals, thereby reducing the simultaneity of the resulting current components to give another means of controlling the speed/noise trade-off. However, without means to assure that these time-separated current pulses remain blended (through variation of supply voltage, temperature, and process) into a smoothly ramped homogeneous composite waveform, the result is current variations as each stage kicks in which again results in less than optimal speed/noise trade-off. As described in further detail below, what is needed is a means for these multiple stages to interact so as to smooth out and minimize ripples in the composite current waveform. Finally, the prior art does not address the issue of cross-coupled noise-sources, see C above. That is, the interaction between noisy power networks connected to output driver transistors, and quiet power networks connected to noise-sensitive parts of the chip such as input buffers, sense amplifiers, or timing generators needs to be addressed. Noise from the output driver transistors is coupled into the common chip substrate mainly through either ohmic or diode connections to the noisy power busses (substrate ties and drain to substrate junctions respectively), or directly from circuitry powered by those quiet power supplies, such as the output buffer pre-drivers. The common substrate resistively couples energy from the large voltage excursions experienced by noisy-power-pin inductances through the common substrate into nearby quiet power busses. I/O buffer pre-driver circuits inject current directly into the quiet power rails which supply those circuits. Together these can cause significant ripple through the package inductance of quiet power pins as well, resulting in misbehavior of noise-sensitive circuitry if not controlled by the buffer design.
The prior art in FIG. 1 shows a buffer which attempts to control the rates of turn-on and turn-off of output drivers by using resistors in series with both the source and drain terminals of the pre-drivers which control the output drivers' gates. Here, the cross-connection between pre-drivers forces faster turn-off than turn-on of the driver transistors. This minimizes crowbar current, but necessarily results in slower switching speed due to the delayed turn-on event. The resistors cause the pre-drivers to produce exponentially decaying voltage waveforms, which results in a time derivative (current slope and inductive noise) which is also exponentially decaying: the turn-on of the output driver begins with a performance-limiting noise peak which immediately begins to decay, contributing ever-less to the charging rate of the output load.
The prior art in FIG. 2 shows a buffer to which an output-enable signal has been added. It also uses resistors in the pre-drivers, resulting in disadvantageous exponential waveforms similar to those produced by the buffer in FIG. 1. Crowbar current avoidance has again been emphasized at the expense of speed, since driver turn-off must occur in this buffer before driver turn-on.
The prior art in FIG. 3 illustrates a modification for making the driver turn-on voltage ramp rate linear rather than exponential, by using a current mirror as a constant-current source to linearly charge the driver gate capacitance. One drawback to this technique is that the current mirrors introduce a DC current path between the power supplies, making it unattractive for applications requiring essentially zero standby current. Another drawback is that the linear voltage ramp applied to the gate of the driver MOSFET does not produce a linear ramp in its drain current: An ideal MOSFET is a square-law device. Its drain current increases in proportion to the square of its gate voltage when in saturation.
The prior art in FIG. 4 shows a buffer with an enable input which again uses resistors in the pre-drivers to control the turn-on rate to be slower than the turn-off rate, with the disadvantages mentioned above. Additional resistors have been added in series with the drains of the output driver transistors to stabilize the output impedance. This reduces impedance variation due to MOSFET manufacturing tolerances (e.g. channel length, threshold, gate oxide thickness). There are several disadvantages however: the added resistance delays the output when driving a capacitive load due to the additional RC time constant; and the voltage drop due to DC load current through the resistors impairs its ability to attain sufficient steady-state voltage levels required by interface standards such as TTL.
The prior art in FIG. 5 shows a composite buffer created essentially by connecting two output buffers in parallel to the same output pin. One of the two sets of drivers (the one with smaller drive current) is turned on or off quickly by a fast pre-driver. The larger parallel driver is turned on at a later time by a delayed pre-driver. This produces a somewhat slower buffer due to the delayed turn on of the larger driver stage, in exchange for somewhat less peak noise: it produces a succession of smaller noise spikes instead of the single larger spike produced by other prior-art buffers. Unfortunately, the time delay between the activation of successive stages (and successive noise spikes) is largely wasted, since it does not contribute to hastening the slew rate of the load.
A problem common to all of the above examples is this: the turn-off of their large, high-capacitance output driver gates must be accomplished very quickly, as this paces the overall switching speed of the composite buffer. This rapid turn-off requires that a rapid spike of discharge current be injected through the pre-driver into a power supply rail to discharge this gate capacitance. Often a limited availability of package pins dictates that the power supply rail and common substrate connections for the pre-drivers must be shared among many other output buffer pre-drivers and also among other internal circuitry of the integrated circuit, such as input buffers. It is usually preferable to connect pre-drivers and input buffers to the "quiet" internal supply rails, since their data and control input signals originate outside the buffer but are referenced to these same quiet supply levels. This assures predictable response of the buffer in the presence of supply noise. However, with common power connections the combined simultaneous switching current from a multitude of such buffer pre-drivers can induce sufficient noise to disturb the operation of other circuits which share these quiet power rails. Thus there remains an un-met need to reduce the initial activation current spike from the pre-drivers.
It would be advantageous if a CMOS buffer could be designed to control power supply noise during transitions of high-drive buffers by tailoring the switching waveforms to produce a speed/noise performance tradeoff very close to the package's theoretical best. It would also be advantageous if the buffer did not require external reference components, or DC current flow to generate reference currents. Further, it would be advantageous if there were no time-wasting active calibration intervals or slew-rate-switching delays.
It would be advantageous if a CMOS buffer could be designed to provide clean output transitions with more stationary output impedances, without entering a high-impedance state prior to any output transition. It would be advantageous if the CMOS output impedance more consistently matched the transmission line load impedance. It would also be advantageous if the buffer could maximize the data-valid interval to provide as much setup and hold time as possible in synchronous systems.
It would be advantageous if the output driver stages were coupled to produce a smooth continuous current waveform rather than the two (or more) distinct current and noise pulses seen in prior art.
It would be advantageous if the switching noise induced into quiet power busses could be reduced by decreasing the rates of change of current through transistors connected to those quiet power busses without sacrificing speed.
Accordingly, a low noise CMOS circuit to provide a constant impedance load and linear ramped current waveform at the circuit output in response to receiving an input signal at a circuit input is provided. The circuit comprises first (Vddp) and second (Vdd) power supply nodes, and first (Vssp) and second (Vss) ground nodes. A first pair of driver transistors are included, with the source of PMOS transistor P5 operatively connected to the first power supply node (Vddp), the drain of said P5 PMOS operatively connected to the output and the drain of NMOS transistor N5, and the source of said N5 NMOS operatively connected to the first ground node (Vssp).
A second pair of driver transistors are operatively connected in parallel to the first transistor pair, with the source of PMOS transistor P6 operatively connected to the first power supply node (Vddp), the drain of said P6 PMOS operatively connected to the output and the drain of NMOS transistor N6, and the source of said N6 NMOS operatively connected to the first ground node (Vssp).
Four pre-driver circuits are included, which each pre-driver circuit including a transistor pair, with the source of a PMOS transistor (P1, P2, P3, and P4) operatively connected to the second power supply node (Vdd), the drain of said PMOS transistors operatively connected to a pre-driver output and the drain of an NMOS transistor (N1, N2, N3, and N4), and the source of said NMOS transistors operatively connected to the second ground node (Vss).
A first pre-driver includes said P1 and N1 transistors, with the gates of said P1 and N1 transistors operatively connected to the circuit input to accept the input signal. The first pre-driver output is operatively connected to the gate of driver PMOS P5 to supply the pdrv1 signal A second pre-driver includes said P2 and N2 transistors, with the gates of said P2 and N2 transistors operatively connected to the circuit input to accept the input signal. The second pre-driver output is operatively connected to the gate of said driver PMOS P6 to supply the pdrv2 signal.
A third pre-driver includes said P3 and N3 transistors, with the gates of said P3 and N3 transistors operatively connected to the circuit input to accept the input signal. The third pre-driver output is operatively connected to the gate of said driver NMOS N6 to supply the ndrv2 signal.
A fourth pre-driver includes said P4 and N4 transistors, with the gates of said P4 and N4 transistors operatively connected to the circuit input to accept the input signal. The fourth pre-driver output is operatively connected to the gate of said driver NMOS N5 to supply the ndrv1 signal.
A first NIMOS (N7) pullup transistor is included, with the drain of N7 NMOS being operatively connected to the second power supply node (Vdd), the source being operatively connected to the gate of P6 PMOS, and the gate being operatively connected to the gate of N5 NMOS gate.
A second NMOS (N8) pullup transistor is included, with the drain of N8 NMOS being operatively connected to the second power supply node (Vdd), the source being operatively connected to the gate of P5 PMOS gate, and the gate being operatively connected to the gate of N5 s NMOS.
Finally, a first PMOS (P7) pulldown transistor is included, with the source of P7 PMOS being operatively connected to the gate of N6 NMOS, the drain being operatively connected to the second ground node (Vss), and the gate being operatively connected to the gate of N5 NMOS, whereby the circuit minimizes the generation of noise at the power nodes, ground nodes, and circuit output.
In some aspects of the invention, a first resistor having a first node is operatively connected to the source of third pre-driver P3 PMOS and the first N7 NMOS pullup transistor drain, and a second node is operatively connected to the second power supply node (Vdd). A second resistor having a first node is operatively connected to the source of the second pre-driver N2 NIMOS and the first P7 PMOS pulldown transistor drain, and a second node is operatively connected to the second ground node (Vss).